(a) Field of the Invention
The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device which can improve write/erase characteristics by decreasing a barrier height.
(b) Description of the Prior Art
In a floating gate type nonvolatile memory, an electrically isolated floating gate electrode is provided under a control gate electrode, and charges in the floating gate electrode are controlled by the control gate electrode so as to store them as data. In a nonvolatile memory of this type, an erase voltage (injection of electrons into the floating gate electrode) and a write voltage (extraction of electrons from the floating gate electrode) for erasing/writing are effected through a tunnel current flowing in a gate oxide film, which is dependent upon an electric field between the floating gate electrode and the drain region. Thus, data write/erase is easier with a thin gate oxide film.
When an electric field is constant, the tunnel current is determined by the barrier height of a thin silicon oxide film. In the case of a conventional thin silicon dioxide film, the barrier height is about 3.2 eV. Assuming that the thickness of the silicon dioxide film is set to be 200 .ANG. and a write/erase pulse width is set at 1 msec., a relatively high write voltage of about 24 V (a voltage applied to the drain for shifting Vth to extract electrons from the floating gate electrode) of an EEPROM cell is required, and an erase voltage of about 24 V (a voltage applied to the control gate electrode for shifting Vth to inject electrons into the floating gate electrode) is also required.
In this manner, when the EEPROM cell requires a high voltage, not only the EEPROM cell itself but also peripheral elements must be able to withstand a high voltage. Thus, the manufacturing process and circuit configuration are complex, resulting in poor density, reliability, and performance. Therefore, the write and erase voltages must be decreased.